This invention relates to internal test structures for testing an integrated circuit, and more particularly to an interface between operational circuitry and primary pins or other operational circuitry of an IC, the interface receiving a test signal from an internal test matrix.
Complex integrated circuits (i.e., VLSI) conventionally include internal test structures. Such test structures access test points which are coupled to operational circuitry. To test a complex integrated circuit (i.e., VLSI) test signals typically are applied to select test points, while responses are sensed from other select test points. According to a conventional "SCAN" approach, one or more primary pins are used for entering test signals to shift registers, which then are relayed to select internal storage elements through test points. See "Design For Testability - A Survey" by T.W. Williams and K.P. Parker, Proceedings IEEE. Vol. 71, pp. 98-112, January 1983; and "A Logic Design Structure For LSI Testing" by E.B. Eichelberger and T.W. Williams, Proceedings 14th Design Automation Conference, June 1977 77CH1216-1C, pp. 462-468. Also see "Built-in Self-Test Techniques" and "Built-in Self-Test Structures" by E.J. McCluskey, IEEE Design and Test, Vol. 2, No. 2, pp. 437-452. Also see U.S. Pat. Nos. 3,806,891 (Eichelberger et. al.); 3,761,675; 4,293,919 (Dasgupta et. al.) and 4,513,418 (Bardell, Jr. et. al.) assigned to the IBM Corporation which disclose the serial connection of flip-flops into a shift register to allow access to them through "fewer" test points.
Such scan structures are complex requiring significant chip area. Also, long serial input sequences are required to implement a test. As a result, test operations require long time periods. Accordingly, there is a need for an alternative interface structure between the primary pins of an lC and the operational circuitry which provides minimal area overhead and allows efficient communication speeds.
According to another test approach a grid-based test structure is integrated into the IC with the operational circuitry. Such a structure is described in commonly-assigned U.S. Pat. No. 4,749,947 issued Jun. 7, 1988 for GRID-BASED, "CROSS-CHECK" TEST STRUCTURE FOR TESTING INTEGRATED CIRCUITS. Such test structure enables access to internal operational circuit elements which are not directly accessible through the IC's primary pins. To further ease the test process, a programmable interface structure is needed which enables the test structure to access circuits at the operational circuitry boundary (e.g., circuit elements directly coupled to the primary pins). Further, a programmable interface for routing test responses off-chip through primary output pins is needed.